Non-volatile storage device and control method thereof

ABSTRACT

A memory card ( 100 ) is comprised of: a flash memory ( 120 ) that includes a plurality of physical blocks ( 122 ) made up of a plurality of pages for storing data and a page register ( 121 ) that holds data to be written to a page; and a controller ( 110 ) that specifies and erases an invalid physical block with reference to a valid block table ( 114 ) indicating whether valid data is stored in each of the physical blocks ( 122 ), when data is written, and that transfers, at the same time, the data to be written to the page register ( 121 ) while carrying out said erasure.

TECHNICAL FIELD

The present invention relates to a nonvolatile storage device utilizinga semiconductor memory, and a control method thereof.

BACKGROUND ART

A storage device that has recently come to be used as a storage of aportable device handling audio data and video data, is equipped with anonvolatile memory such as a flash memory that is updatable, highlyportable, and does not require battery backup, and the like.

FIG. 1 is a block diagram showing the structure of a memory card that isan existing nonvolatile storage device.

A memory card 300, which is a device for storing data, being connectedto a host apparatus 200 such as a personal computer and a digitalcamera, includes a controller 310 and a flash memory 320. The hostapparatus 200 writes and reads data to and from the memory card 300, byuse of a card control signal and a card data signal. Such card controlsignal and card data signal are inputted/outputted between the hostapparatus 200 and the controller 310 inside the memory card 300.

Regarding data writing and reading performed between the controller 310and the flash memory 320, the controller 310 writes and reads data toand from the flash memory 320 by use of the memory control signal andmemory data signal. Note that the flash memory 320 connected to thecontroller 310 does not have to be one chip, and therefore that pluralchips may be connected to the controller 310.

FIG. 2 is a block diagram showing the configuration of the controller310.

The controller 310 is comprised of an MPU 311, a page RAM 312, anaddress conversion table 313, and an erase block table 314.

The MPU 311 has an overall control over the controller 310, as well ascontrolling the data erasure from, data writing to, and data readingfrom the flash memory 320. The page RAM 312 is a volatile memory fortemporarily storing data handled between the host apparatus 200 and theflash memory 320. The address conversion table 313 is a table for makinga conversion between a host apparatus 200-specified address of data thatis written to the flash memory 320 and a physical address in the flashmemory 320. The erase block table 314 is a table that indicates, on aphysical address basis, whether physical blocks in the flash memory 320have already been erased or written. Information stored in the addressconversion table 313 and the erase block table 314 is generated byreading out data of all the physical blocks in the flash memory 320 atthe power-on time.

FIG. 3 is a block diagram showing the configuration of the flash memory320.

The flash memory 320 is comprised of a page register 321, a memory cellarray 323, a row decoder 324, and a command decoder 325.

The memory cell array 323 is made up of all the memory cells containedin one chip of the flash memory 320. Memory cells constitute a page inunits in which reading and writing can be performed simultaneously.Furthermore, a plurality of pages make up a physical block 322 that isan erasure unit. The page register 321 has the capacity equivalent topages of memory cells, and holds write data to be inputted from thecontroller 310 and read data to be read out from memory cells. The rowdecoder 324 selects a page specified by the controller 310 at the timeof data reading and writing, whereas it selects a physical block 322specified by the controller 310 at the time of erasing data. The commanddecoder 325 executes a command from the controller 310 that is sent as amemory control signal.

FIG. 4 is a schematic diagram showing example correspondence among dataelements stored in the address conversion table 313, the erase blocktable 314, and the flash memory 320.

Data in address 0 described in the address conversion table 313 is aphysical address that corresponds to logical address 0. Since such datais “0001” in an example illustrated in FIG. 4(a), it indicates that datain logical address 0 is written in physical address 1 in the flashmemory 320. Meanwhile, “FFFF” indicating a physical address thatcorresponds to logical address 1 is an invalid value that means thatthere is no data in logical address 1. Here, “invalid value” is anarbitrary value that indicates invalidity and that is defined as invalidunder the address conversion rule. An example of such value is a fixedvalue “0” and the maximum value “65535” in the case of 16-bit data.Furthermore, since data in address 2 in the address conversion table 313is “0002”, it indicates that data in logical address 2 is written inphysical address 2 in the flash memory 320.

Meanwhile, the erase block table 314 shows the state of the respectivephysical blocks in the flash memory 320. The erase block table 314holds, as address values, values that correspond to the respectivephysical addresses in the flash memory 320, and holds, as data values,whether the respective physical blocks in the flash memory 320 havealready been erased or written. For example, the erase block table 314holds the value 1 when a physical block has already been erased, whereasit holds the value 0 when a physical block has already been written.Stated another way, data in address 0 in the erase block table 314indicates whether a physical block corresponding to physical address 0in the flash memory 320 has already been erased/written. Since such datais “1” in an example illustrated in FIG. 4(a), it indicates that thephysical block corresponding to physical address 0 has already beenerased. Similarly, since each data in addresses 1 and 2 in the eraseblock table 314 is “0”, it indicates that the physical blockscorresponding to the respective physical addresses 1 and 2 in the flashmemory 320 have already been written.

Next, a description is given of the operation to be performed when datain the existing memory card 300 with the above structure is updated bythe host apparatus 200. FIG. 5 is a timing chart showing a writeoperation to be performed in such case, whereas FIG. 6 Is a timing chartshowing an erase operation to be performed in such case. In therespective timing charts shown in FIGS. 5 and 6, upper signals are thecard control signal and card data signal shown in FIG. 1, indicatingthat data is inputted from the host apparatus 200 to the memory card300. Middle signals are the memory control signal and memory data signalshown in FIG. 3, indicating that data is inputted from the controller310 to the flash memory 320. A lower signal is a memory control signal,indicating that data is outputted from the flash memory 320 to thecontroller 310. Here, a description is given for the case as an examplewhere data in logical address 0 in the memory card 300 is updated, inthe state shown in FIG. 4(a).

First, the host apparatus 200 sends, to the memory card 300, a writecommand 401 for logical address 0 as the card control signal at timet421, and starts transferring the write data as the card data signal attime t422. Such write data is to be stored into the page RAM 312 of thecontroller 310 in the memory card 300.

Upon receipt of the write command 401 from the host apparatus 200, thecontroller 310 searches the erase block table 314 for an already erasedphysical block 322 to which it is possible to write the data. Thecontroller 310 detects from the erase block table 314 that a physicalblock in physical address 0 is an already erased physical block 322.

After the data transfer from the host apparatus 200 is finished, thecontroller 310 sends a write address specification command 403 for thisdata at time t423, so as to indicate the flash memory 320 that the writeaddress is to be inputted thereafter. The command decoder 325 decodesthe write address specification command 403, and controls the rowdecoder 324 to make it obtain the address to be inputted thereafter.

The controller 310 sends a write address 404 to the flash memory 320 attime t424. The row decoder 324 obtains the inputted write address, andselects a specified page so that the data can be written to it. Next,the command decoder 325 recognizes that the write address has beenobtained, and controls the page register 321 to obtain the write addressto be inputted thereafter.

Next, the controller 310 starts transferring the write data 405 from thepage RAM 312 to the flash memory 320 at time t425. The command decoder325 stores the inputted write data into the page register 321.

Then, the controller 310 sends a write execute command 406 to the flashmemory 320 at time t427.

In response to this, the command decoder 325 starts, at time t427,writing the data stored in the page register 321 to memory cells of apage selected by the row decoder 324. At the same time, the commanddecoder 325 sends, to the controller 310, a write busy 407 as the memorycontrol signal indicating that writing is ongoing. A period defined asthe write busy 407 indicates that no data shall be allowed to be newlyread out, written, or erased during such period. This is because thecommand decoder 325 does not allow any commands to be inputted from thecontroller 310 for the reason that the same page that is subject towriting needs to remain selected by the row decoder 324 while suchwriting is taking place.

According to a general specification, “erase” and “write” operations tobe performed on the flash memory 320 complete separately and thereforeno command is to be written while writing and erasure are in busy state(e.g. NH29W12811T datasheet of Hitachi Ltd.)

Next, after the write operation to the page is finished at time t428,the command decoder 325 releases the write busy 407 of the memorycontrol signal. From then on, it is possible for commands to be inputtedfrom the controller 310.

After this, the controller 310 writes, to the other pages of thephysical block 322 to which the above writing has been performed, datatransferred from the host apparatus 200 in the above-described manner.

After the data writing is finished as in the above manner, thecontroller 310 obtains, from the address conversion table 313, aphysical block in which the data in logical address 0 subject to thewriting, was originally written. Since data in address 0 in the addressconversion table 313 is “0001” in an example shown in FIG. 4(a), thephysical block corresponding to physical address 1 is the location wherethe old data was written.

Then, in order to erase the old data which became invalid due to thewriting performed this time, the controller 310, as shown in FIG. 6,sends an erase address specification command 411 for the physical block322 corresponding to physical address 1 at time t431, so as to indicatethe flash memory 320 that the erase address is to be inputtedthereafter. The command decoder 325 decodes the erase addressspecification command 411, and controls the row decoder 324 to obtainthe address to be inputted thereafter.

The controller 310 sends an erase address 412 to the flash memory 320 attime t432. The row decoder 324 obtains the inputted erase address, andselects a specified physical block 322 so that the data can be erased.

Next, the controller 310 sends an erase execute command 413 to the flashmemory 320 at time t433.

In response to this, the command decoder 325 starts, at time t434,erasing the physical block 322 selected by the row decoder 324. At thesame time, the command decoder 325 sends, to the controller 310, anerase busy 414 as the memory control signal indicating that erasure isongoing. A period defined as the erase busy 414 indicates that no datashall be allowed to be newly read out, written, or erased during suchperiod, as in the case of writing.

Next, after the erase operation on the physical block 322 is finished attime t435, the command decoder 325 releases the erase busy 414 of thememory control signal.

Then, the MPU 311 of the controller 310 updates the address conversiontable 313 and erase block table 314. FIG. 4(b) is a schematic diagramshowing the state changed from the state shown in FIG. 4(a) by updatingthe data in logical address 0.

More specifically, since physical block 322 to which the writing wasperformed this time is in address 0, the MPU 311 updates the data inaddress 0 in the erase block table 314 to “0” indicating that the blockhas already been written. Moreover, as shown in FIG. 4(b), the MPU 311also updates the value of address 0 in the address conversion table 313to “0000” that indicates the physical address of the physical block 322to which the writing has performed this time. Furthermore, since thephysical block 322 which was erased this time is in address 1, the MPU311 updates the data in address 1 in the erase block table 314 to “1”indicating that the block has already been erased, as shown in FIG.4(b).

Data in the memory card 300 is updated by the host apparatus 200, as inthe above-described manner.

Note that in FIGS. 5 and 6, although time widths are representeddifferently from the actual times for simplification purposes, itactually takes a few ms until an erase busy 414 and a write busy 407 end(e.g. according to NH29W12811T data sheet of Hitachi Ltd., erase busytime is 1 ms and write busy time is 2.5 ms). Furthermore, it takes a fewhundred μs to input write data 405 (e.g. a value calculated from theNH29W12811T datasheet is: cycle time 120 ns×2112 bytes=253.44 μs), whichis extremely long compared with other command inputs and address inputsthat require less than 1 μs.

In other words, time required for update is approximately equal to thetotal of erase busy 414, time required to input write data 405, andwrite busy 407.

As described above, when data is updated in the existing memory card300, new data is written to an already erased physical block 322, andthen a physical block 322 which has become old data due to such writingis erased. This is because, if new data were written to a physical block322 that contains original data after such physical block 322 is erased,there would be the state in which the original data has already beenerased and the new data has not yet been written, for example, when someabnormality occurred during data processing, which causes a possibilityof data destruction from the viewpoint of the host apparatus.

However, when data is updated in the existing memory card 300, there issuch a problem as the duplication of the same data from the standpointof the host apparatus in which new data has already been written and aphysical block 322 which became old data has not yet been erased, whensome abnormality occurs in the stage where such new data has beenwritten to an already erased physical block 322.

Furthermore, when data is updated in the existing memory card 300, thereexists a period during which the next command cannot be inputted fromthe controller 310 to the flash memory 320 while erasure is ongoing.This causes time required for update to get longer.

Moreover, when the capacity of the memory card 300 becomes lager, thecapacity of the address conversion table 313 and erase block table 3l14also becomes larger, which further leads to an increased capacity of theRAM of the controller 310 in which these tables are generated.

The present invention has been conceived in view of the abovecircumstances, and it is an object of the present invention to provide anonvolatile storage device and a control method thereof capable ofmaintaining data consistency even when some abnormality occurs whiledata is being updated, as well as capable of shortening the timerequired for updating data.

DISCLOSURE OF INVENTION

In order to achieve the above object, the nonvolatile storage deviceaccording to the present invention is a nonvolatile storage devicecomprising: a nonvolatile storage unit having a plurality of physicalblocks, each of which is made up of a plurality of pages for storingdata; and a control unit operable to write, when updating the datastored in the storage unit, new data to an erased first physical blockthat is different from a second physical block in which old data isstored, wherein when updating the data stored in the storage unit, thecontrol unit writes the new data to a page of the first physical blockafter erasing invalid data stored in said first physical block.

Accordingly, it becomes possible to maintain data consistency, even whensome abnormality occurs while the operation of data rewiring is beingperformed.

Here, it is preferable that the storage unit includes: a specificationunit operable to select and specify one of the pages or one of theplurality of physical blocks; and a page holding unit operable to hold,in advance, data to be written to said one of the pages, and whenupdating the data stored in the storage unit, the control unit (i)erases the invalid data stored in the first physical block specified bythe specification unit, (ii) transfers, to the page holding unit, thenew data, while said erasure is being executed, and (iii) writes the newdata to said first physical block after the erasure is finished.

In this case, since it is possible to transfer, to the page holdingunit, the new data to be written while the physical block is beingerased, it becomes possible to update the data stored in the storageunit, consuming a shorter time required for transferring the write data.

Furthermore, the storage unit may include a plurality of storage areas,each of which has a management area and a data area, the management areamay have an address conversion table and a valid block table whichcorrespond to one of the storage areas which said management areabelongs to, the address conversion table being used to make a conversionbetween a logical address and a physical address, and the valid blocktable indicating whether valid data is stored in the respective physicalblocks, and the control unit may further include a table holding unitoperable to hold the address conversion table and the valid block table.

Accordingly, it is not necessary for the table holding unit of thecontrol unit to hold address conversion tables and valid block tablesfor all the storage areas, which requires the table holding unit to haveonly a small capacity.

Note that not only is it possible to embody the present invention as anonvolatile storage device with the above configuration, but also as anonvolatile memory and a control device thereof. Moreover, it is alsopossible to embody the present invention as a control method for anonvolatile storage device that includes, as its steps, thecharacteristic units equipped to the nonvolatile storage device with theabove configuration, and further as a program that causes a computerapparatus to execute these steps.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a structure of a memory card that isan existing nonvolatile storage device;

FIG. 2 is a block diagram showing a configuration of a controller of theexisting memory card;

FIG. 3 is a block diagram showing a configuration of a flash memory ofthe existing memory card;

FIG. 4 is a schematic diagram showing example correspondence among dataelements stored in an address conversion table, an erase block table,and the flash memory of the existing memory card;

FIG. 5 is a timing chart showing a write operation to be performed whendata is updated in the existing memory card;

FIG. 6 is a timing chart showing an erase operation to be performed whendata is updated in the existing memory card;

FIG. 7 is a block diagram showing a structure of a memory card that isan embodiment of the nonvolatile storage device according to the presentinvention;

FIG. 8 is a block diagram showing a configuration of a controlleraccording to the present embodiment;

FIG. 9 is a block diagram showing a configuration of a flash memoryaccording to the present embodiment;

FIG. 10 is a schematic diagram showing an example logical configurationinside a memory cell array of the flash memory according to the presentembodiment;

FIG. 11 is a schematic diagram showing example correspondence among dataelements stored in an address conversion table, a valid block table, andthe flash memory according to the present embodiment;

FIG. 12 is a flowchart showing an operation to be performed in thecontroller when data is updated in the memory card according to thepresent embodiment; and

FIG. 13 is a timing chart showing an operation to be performed when datais updated in the memory card according to the present embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

The following describes an embodiment of the present invention withreference to the drawings.

FIG. 7 is a block diagram showing the structure of a memory card that isan embodiment of the nonvolatile storage device according to the presentinvention.

A memory card 100, which is a device for storing data, being connectedto a host apparatus 200 such as a personal computer and a digitalcamera, includes a controller 110 and a flash memory 120. The hostapparatus 200 writes and reads data to and from the memory card 100, byuse of a card control signal and a card data signal. Such card controlsignal and card data signal are inputted/outputted between the hostapparatus 200 and the controller 110 inside the memory card 100.

Regarding data writing and reading performed between the controller 110and the flash memory 120, the controller 110 writes and reads data toand from the flash memory 120 by use of the memory control signal andmemory data signal. Note that the flash memory 120 connected to thecontroller 110 does not have to be one chip, and therefore that pluralchips may be connected to the controller 110.

FIG. 8 is a block diagram showing the configuration of the controller110.

The controller 110 is comprised of an MPU 111, a page RAM 112, anaddress conversion table 113, and a valid block table 114.

The MPU 111 has an overall control over the controller 110, and alsocontrols the data erasure from, data writing to, and data reading fromthe flash memory 120. The page RAM 112 is a volatile memory fortemporarily storing data handled between the host apparatus 200 and theflash memory 120. The address conversion table 113 is a table for makinga conversion between a host apparatus 200-specified address of data thatis written to the flash memory 120 and a physical address in the flashmemory 120. The valid block table 114 is a table that indicates whetherdata written on the flash memory 120 is valid or invalid on a physicaladdress basis.

Here, “invalid physical block” means that valid data is not written tosuch block, and such physical block can either be in already writtenstate or already erased state. Furthermore, information in the addressconversion table 113 and the valid block table 114 is written in themanagement areas in the flash memory 120, and is read out by the MPU 111from the flash memory 120 after the power is turned on or when necessaryso as to be stored into the address conversion table 113 and the validblock table 114. Moreover, when the address conversion table 113 and thevalid block table 114 are updated, the MPU 111 writes the updated datato the management areas in the flash memory 120, in response to suchupdate.

FIG. 9 is a block diagram showing the configuration of the flash memory120.

The flash memory 120 is comprised of a page register 121, a memory cellarray 123, a row decoder 124, and a command decoder 125.

The memory cell array 123 is made up of all the memory cells containedin one chip of the flash memory 120. Memory cells constitute a page inunits in which reading and writing can be carried out simultaneously.Furthermore, a plurality of pages make up a physical block 122 that isan erasure unit. The page register 121 has the capacity equivalent topages of memory cells, and holds write data to be inputted from thecontroller 110 as well as read data to be read out from memory cells.

The row decoder 124 selects a page specified by the controller 110 atthe time of data reading and writing, whereas it selects a physicalblock 122 specified by the controller 110 at the time of erasing data.The command decoder 125 executes a command from the controller 110 thatis sent as a memory control signal. Furthermore, the command decoder 125allows a command to be inputted from the controller 110 to the flashmemory 120 even while data erasure is ongoing, and exercises a controlso that the command decoder 125 can operate even when commands come inthe order of “write data” and “write address”.

FIG. 10 is a diagram showing an example logical configuration inside thememory cell array 123 of the flash memory 120.

The memory cell array 123 is divided into plural areas in address order(four areas in an example shown in FIG. 10), and each of such areas hasa management area and a data area. The address conversion table 113 andthe valid block table 114 of the controller 110 are tables that describeinformation of one such area. Stated another way, an addressconversation table 113 and a valid block table 114 corresponding to anarea to which each management area belongs to is written in suchmanagement area.

FIG. 11 is a schematic diagram showing example correspondence among dataelements stored in the address conversion table 113, the valid blocktable 114, and the flash memory 120.

Data in address 0 described in the address conversion table 113 is aphysical address that corresponds to logical address 0. Since such datais “0001” in an example illustrated in FIG. 11(a), it indicates thatdata in logical address 0 is written in physical address 1 in the flashmemory 120. Meanwhile, “FFFF” indicating a physical address thatcorresponds to logical address 1 is an invalid value that means thatthere is no data in logical address 1. Here, “invalid value” is anarbitrary value that indicates invalidity and that is defined as invalidunder the address conversion rule. An example of such value is a fixedvalue “0” and the maximum value “65535” in the case of 16-bit data.Furthermore, since data in address 2 in the address conversion table 113is “0002”, it indicates that data in logical address 2 is written inphysical address 2 in the flash memory 120.

Meanwhile, the valid block table 114 shows the state of data written tothe flash memory 120. The valid block table 114 holds, as addressvalues, values that correspond to the respective physical addresses inthe flash memory 120, and holds, as data values, whether data written tothe respective physical addresses in the flash memory 120 is valid dataor invalid data. For example, the valid block table 114 holds the value0 when such data is valid, whereas it holds the value 1 when such datais invalid. Stated another way, data in address 0 in the valid blocktable 114 indicates whether data in physical address 0 in the flashmemory 120 is valid or invalid. Since such data is “1” in an exampleillustrated in FIG. 11(a), it indicates that data in physical address 0is invalid. Similarly, since each data in addresses 1 and 2 in the validblock table 114 is “0”, it indicates that data in the respectivephysical addresses 1 and 2 in the flash memory 120 is valid.

Next, a description is given of the operation to be performed when datain the memory card 100 with the above structure is updated by the hostapparatus 200. FIG. 12 is a flowchart showing an operation to beperformed in the controller 110 in such case, whereas FIG. 13 is atiming chart showing an operation to be performed in such case. In thetiming chart shown in FIG. 13, upper signals are the card control signaland card data signal shown in FIG. 7, indicating that data is inputtedfrom the host apparatus 200 to the memory card 100. Middle signals arethe memory control signal and memory data signal shown in FIG. 3,indicating that data is inputted from the controller 110 to the flashmemory 120. A lower signal is a memory control signal, indicating thatdata is outputted from the flash memory 120 to the controller 110. Here,a description is given for the case as an example where data in logicaladdress 0 in the memory card 100 is updated, in the state shown in FIG.11(a).

First, the host apparatus 200 sends, to the memory card 100, a writecommand 301 intended for logical address 0 as the card control signal attime t321, and starts transferring write data as the card data signal attime t322. Such write data is to be stored into the page RAM 112 of thecontroller 110 in the memory card 110.

Upon receipt of the write command 301 from the host apparatus 200, thecontroller 110 searches the valid block table 114 for a physical blockstoring invalid data to which it is possible to write the data (StepS101). Upon detecting in the valid block table 114 that physical address0 is a physical block 122 storing invalid data, the controller 110sends, to the flash memory 120, an erase address specification command303 for the physical block 122 corresponding to physical address 0 attime t322. Such erase address specification command 303 indicates thatthe erase address is to be inputted thereafter. The command decoder 125decodes the erase address specification command 303, and controls therow decoder 124 to make it obtain the address to be inputted thereafter.

Next, the controller 110 sends an erase address 304 to the flash memory120 at time t323. The row decoder 124 obtains the inputted eraseaddress, and selects a specified physical block 122 so that the data canbe erased.

Then, the controller 110 sends an erase execute command 305 to the flashmemory 120 at time t324 (Step S102).

In response to this, the command decoder 125 starts, at time t325,erasing the physical block 122 selected by the row decoder 124. At thesame time, the command decoder 125 sends, to the controller 110, anerase busy 306 as the memory control signal indicating that erasure isongoing. During the period defined as the erase busy 306, no data shallbe allowed to be newly read out from, written to, or erased from aphysical block 122 which are operations that require a selection by therow decoder 124, since the row decoder 124 needs to continuously selectthe physical block 122 subject to erasure.

After the data transfer from the host apparatus 200 is finished, thecontroller 310 sends a write data input command 307 to the flash memory120 at time t326, regardless of whether or not the erase busy 306 isinputted from the flash memory 120 as the memory control signal, so asto indicate the flash memory 120 that write data is to be inputtedthereafter. The command decoder 125 decodes the write data input command307, and controls the page register 121 to make it obtain the write datato be inputted thereafter.

Next, the controller 110 starts transferring write data 308 from thepage RAM 112 to the flash memory 120 at time 327t (Step S103). Thecommand decoder 125 stores the inputted write data into the pageregister 121. The data transferred here is write data to be written to apage included in the physical block 122 that is being erased. Note thatthe flash memory 120 is performing erase operation here, but it ispossible to store write data since the page register 121 is not in use.

After the erase operation performed on the physical block 122 isfinished at time t328, the command decoder 125 releases the erase busy306 of the memory control signal. From then on, It is possible for therow decoder 124 to select another physical block 122 or page.

After the transfer of the write data from the page RAM 112 to the flashmemory 120 is finished and the erase busy 306 from the flash memory 120is released (Steps S104 and S105), the controller 110 sends a writeaddress specification command 309 for the data transferred to the pageregister 121 at time t328, so as to indicate the flash memory 120 that awrite address is to be inputted thereafter. The command decoder 125decodes the write address specification command 309, and controls therow decoder 124 to obtain the address to be inputted thereafter.

The controller 110 sends a write address 310 to the flash memory 120 attime t329. The row decoder 124 obtains the inputted write address, andselects a specified page so that the data can be written to it. The pageto be specified here is a page included in the physical block on whichthe erase operation has finished above.

Then, the controller 110 sends a write execute command 311 to the flashmemory 120 at time t330 (Step 5106).

In response to this, the command decoder 125 starts, at time t331,writing the data stored in the page register 121 to memory cells in thepage selected by the row decoder 124. At the same time, the commanddecoder 125 sends, to the controller 110, a write busy 312 as the memorycontrol signal indicating that writing is ongoing. During a perioddefined as the write busy 312, the row decoder 124 keeps selecting apage to which data is to be written, and therefore no data shall beallowed to be newly read out from, written to, or erased from a physicalblock 122, which are operations that require a selection by the rowdecoder 124, as in the case of the period of the erase busy 306.

After the write operation to the page is finished at time t332, thecommand decoder 125 releases the write busy 312 of the memory controlsignal.

After this, the controller 110 writes the data transferred from the hostapparatus 200, to the other pages of the physical block 122 which hasbeen erased in the above-described manner.

Then, the MPU 111 of the controller 110 updates the address conversiontable 113 and valid block table 114 (Step S107). FIG. 11(b) is aschematic diagram showing the state changed from the state shown in FIG.11(a) by updating the data in logical address 0.

More specifically, since the data corresponding to logical address 0which was updated this time is “0001”, as shown in FIG. 11(a), the MPU111 updates the data in the corresponding address 1 in the valid blocktable 114 to “1”, as shown in FIG. 11(b), indicating invalid data.Moreover, the MPU 111 also updates the value of address 0 in the addressconversion table 113 to “0000”, as shown in FIG. 11(b), that indicatesthe physical address of the physical block 122 to which the writing hasperformed this time. Then, the MPU 111 updates the data in address 0 inthe valid block table 114 to “0” indicating valid data, as shown in FIG.11(b).

Finally, the MPU 111 writes the address conversation table 113 and validblock table 114 which have been updated in the above manner, to themanagement areas in the flash memory 120 in updated form.

Data in the memory card 100 is updated by the host apparatus 200 side,as in the above-described manner. Note that when this writing is carriedout, the updated old data of logical address 0 exits in the flash memory120 as invalid data, and will not be erased until writing is performedto the physical block 122 that stores such old data, at the time ofupdating another data.

As described above, when data is updated in the memory card 100, aphysical block 122 storing invalid data is erased first, and then newdata is written to such physical block 122 which has been erased. Thismakes it possible to transfer write data 308 from the page RAM 112 tothe page register 121 in the flash memory 120 even during the period ofthe erase busy 306. Accordingly, it becomes possible to update the flashmemory 120, consuming a shorter time required for transferring writedata.

Moreover, it is also possible to maintain consistency between data evenif some abnormality occurs while the operation for updating data istaking place.

Furthermore, since the memory cell array 123 is logically divided intoplural areas, and an address conversion table 113 and a valid blocktable 141 corresponding to each of such areas are written to themanagement area of each of the areas, the RAM of the controller 110 thatreads in these tables is required to have only a small capacity.

Note that in the present embodiment, the controller 110 sends, to theflash memory 120, the write data input command 307 after the datatransfer from the host apparatus 200 is finished, but the presentinvention is not limited to this. Therefore, the controller 110 may sendthe write data input command 307 after the erase execute command 305 issent and before the data transfer from the host apparatus 200 isfinished, for example. In this case, the controller 110 transfers thewrite data 308 from the page RAM 112 to the flash memory 120 after thedata transfer from the host apparatus 200 is finished.

Moreover, in the present embodiment, a description is given for a methodin which the command decoder 125 exercises such a control as enables theflash memory 120 to operate even if commands are inputted in order of“write data” and “write address”, but the present invention is notlimited to this. It is therefore possible to input commands in order of“write address” and “write data” by newly incorporating an addressregister to the flash memory 120, where a write address to be inputtedduring the period of the erase busy 306 is to be stored, and then bymoving such write address to the row decoder 124 from the addressregister before the writing is executed.

As described above, according to the nonvolatile storage device of thepresent invention, it is possible to maintain consistency between dataeven if some abnormality occurs during the operation for updating datais taking place, since, when data stored in a storage unit is updated,data stored in an invalid physical block that is different from aphysical block in which old data is stored, is erased first and then newdata is written to a page in the erased physical block.

Furthermore, it is also possible to shorten the time required forupdating data, by transferring, to the storage unit, data to be writtennext, in line with the erasure of a physical block. This leads to animproved usability of the nonvolatile storage device, as well as to afurther improved user convenience.

As is obvious from the above, the present invention, which is capable ofimproving the usability of a nonvolatile storage device, is extremelyuseful in the present age when there is a widespread use of portabledevices utilizing nonvolatile storage devices.

Industrial Applicability

As described above, the nonvolatile storage device according to thepresent invention is suited for use as a storage device that stores dataof a portable device, such as a digital camera and a mobile phone, thathandles audio data and video data.

1. A nonvolatile storage device comprising: a nonvolatile storage unithaving a plurality of physical blocks, each of which is made up of aplurality of pages for storing data; and a control unit operable towrite, when updating the data stored in the storage unit, new data to anerased first physical block that is different from a second physicalblock in which old data is stored, wherein when updating the data storedin the storage unit, the control unit writes the new data to a page ofthe first physical block after erasing invalid data stored in said firstphysical block.
 2. The nonvolatile storage device according to claim 1,wherein the storage unit includes: a specification unit operable toselect and specify one of the pages or one of the plurality of physicalblocks; and a page holding unit operable to hold, in advance, data to bewritten to said one of the pages, wherein when updating the data storedin the storage unit, the control unit (i) erases the invalid data storedin the first physical block specified by the specification unit, (ii)transfers, to the page holding unit, the new data, while said erasure isbeing executed, and (iii) writes the new data to said first physicalblock after the erasure is finished.
 3. The nonvolatile storage deviceaccording to claim 2, wherein when writing the new data, the controlunit transfers, to the specification unit, an address for specifying thepage to which the new data is to be written, after transferring said newdata to the page holding unit, and writes the new data to said one ofthe pages selected by the specification unit.
 4. The nonvolatile storagedevice according to claim 1, wherein the storage unit includes aplurality of storage areas, each of which has a management area and adata area, the management area has an address conversion table and avalid block table which correspond to one of the storage areas whichsaid management area belongs to, the address conversion table being usedto make a conversion between a logical address and a physical address,and the valid block table indicating whether valid data is stored in therespective physical blocks, and the control unit further includes atable holding unit operable to hold the address conversion table and thevalid block table.
 5. The nonvolatile storage device according to claim4, wherein the control unit (i) reads out, from the storage unit, theaddress conversion table and valid block table corresponding to each ofthe storage areas when necessary, so as to have the table holding unithold said readout tables, (ii) specifies the first physical block inwhich the invalid data is stored with reference to the valid block tablewhen updating the data stored in the storage unit, (iii) updates theaddress conversion table and the valid block table when said update ofthe data is finished, so as to reflect said update of the data on thesetables, and (iv) writes the updated address conversion table and validblock table to the corresponding management area.
 6. A nonvolatilememory, comprising: a plurality of physical blocks, each of which ismade up of a plurality of nonvolatile pages for storing data; aspecification unit operable to select and specify one of the pages orone of the physical blocks; and a page holding unit operable to hold, inadvance, data to be written to said one of the pages, wherein the datato be written to said page is transferred to the page holding unit whilesaid one of the physical blocks specified by the specification unit isbeing erased.
 7. A control device for controlling a nonvolatile memorythat includes a plurality of physical blocks, each of which is made upof a plurality of nonvolatile pages for storing data, the control devicecomprising a control unit operable to write, when updating the datastored in the nonvolatile memory, new data to an erased first physicalblock that is different from a second physical block in which old datais stored, wherein when updating the data stored in the nonvolatilememory, the control unit writes the new data to a page of the firstphysical block after erasing invalid data stored in said first physicalblock.
 8. The control device according to claim 7, further comprising atable holding unit operable to hold an address conversion table and avalid block table, the address conversion table being used to make aconversion between a logical address and a physical address, and thevalid block table indicating whether valid data is stored in therespective physical blocks, wherein the control unit specifies the firstphysical block in which the invalid data is stored with reference to thevalid block table, when updating the data stored in the nonvolatilememory, and updates the address conversion table and the valid blocktable when said update of the data is finished, so as to reflect saidupdate of the data on these tables.
 9. A control method for controllinga nonvolatile storage device, the control method comprising a controlstep of writing new data to an erased first physical block that isdifferent from a second physical block in which old data is stored, whendata stored in a nonvolatile storage unit having a plurality of physicalblocks is updated, each of said physical blocks being made up of aplurality of pages for storing data, wherein in the control step, whenthe data is updated, the new data is written to a page of the firstphysical block, after invalid data stored in said first physical blockis erased.
 10. The control method for controlling the nonvolatilestorage device according to claim 9, further comprising a table holdingstep of holding an address conversion table and a valid block table, theaddress conversion table being used to make a conversion between alogical address and a physical address, and the valid block tableindicating whether valid data is stored in the respective physicalblocks, wherein the control step includes: a specification step ofspecifying the first physical block in which the invalid data is storedwith reference to the valid block table, when the data stored in thestorage unit is updated; and an update step of updating the addressconversion table and the valid block table when said update of the datais finished, so as to reflect said update of the data on these tables.11. A program for updating data stored in a nonvolatile memory thatincludes a plurality of physical blocks, each of which is made up of aplurality of nonvolatile pages for storing data, the program causing acomputer to execute a control step of writing new data to an erasedfirst physical block that is different from a second physical block inwhich old data is stored, wherein in the control step, when the data isupdated, the new data is written to a page of the first physical block,after invalid data stored in said first physical block is erased.